Is the use of records the solution to all latch problems in VHDL
I was recently told that the solution to all (most) problems with
unintended latches during VHDL synthesis is to put whatever the
problematic signal is in a record.
This seems like it's a little bit too good to be true, but I'm not that
experienced with VHDL so there could be something else that I'm not
considering.
Should I put all my signals in records?
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