FPGA ROM access contention

FPGA ROM access contention

I've written a verilog code to implement AES on Virtex II Pro series FPGA.
Everything is fine before I do timing simulation. I mean I can get the
right encrypted data in function simulation. But in the timing simulation
or download it to FPGA board. The result is not correct any more. And I
try to debug it.
With timing simulation waveform, I found the bug involved with how I
implement SubByte function in AES. I used look up table (ROMs) to
implement it. But the inputs of these 16 ROMs become same. I write the
code for 16 ROMs as follows.
aes_sbox SBOX15 (di[127:120],sb[127:120]);
aes_sbox SBOX14 (di[119:112],sb[119:112]);
aes_sbox SBOX13 (di[111:104],sb[111:104]);
aes_sbox SBOX12 (di[103:96],sb[103:96]);
aes_sbox SBOX11 (di[95:88],sb[95:88]);
aes_sbox SBOX10 (di[87:80],sb[87:80]);
aes_sbox SBOX9 (di[79:72],sb[79:72]);
aes_sbox SBOX8 (di[71:64],sb[71:64]);
aes_sbox SBOX7 (di[63:56],sb[63:56]);
aes_sbox SBOX6 (di[55:48],sb[55:48]);
aes_sbox SBOX5 (di[47:40],sb[47:40]);
aes_sbox SBOX4 (di[39:32],sb[39:32]);
aes_sbox SBOX3 (di[31:24],sb[31:24]);
aes_sbox SBOX2 (di[23:16],sb[23:16]);
aes_sbox SBOX1 (di[15:8],sb[15:8]);
aes_sbox SBOX0 (di[7:0],sb[7:0]);
I used different bits to be inputs to different ROM. But in the timing
simulation, all of 16 byte inputs become the value of the least
significant byte. It just like I connected every ROM input with di[7:0].
So the output of these 16 ROMs are same. You can see the waveform below.
Pay attention to the signal 'sb'. It is 128 bit (16bytes), but every byte
is same with each other.
For example, sb is 128'h8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c. But the correct
one should be 128'h63cab7040953d051cd60e0e7ba70e18c. Please pay attention
to the last byte of correct value and wrong value. They are same. It just
like I copied 16 times.
And if I don't use ROMs to implement SubBytes function. It can get a
correct result from timing simulation and board. So I am sure the only
problem is those ROMs.
Also, it is not a problem of clock period. Cause the critical path delay
of this circuit is 13ns. And my clock period is 40ns. I tried to change
the clock period to 400ns. The bug is still there.
It seems that it is ROM access contention issue. But I don't know how to
fix it.